Exploring the performance of partially reconfigurable point-to-point interconnects

Abdali, El Mehdi;Pelcat, Maxime;Berry, Francois;Diguet, Jean-philippe;Palumbo, Francesca

2017-01-01

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Abstract

An ever larger share of FPGAs are supporting Dynamic and Partial Reconfiguration (DPR). A reconfigurable point-to-point interconnect (Ï -P2P) is a communication mechanism based on DPR that swaps between different precomputed configurations stored in partial bitstreams. Ï -Point-to-Point (P2P) is intended as a lightweight interconnect that suits the reconfigurable systems where a limited number of configurations are desirable. This paper assesses the pros and cons of Ï -P2P in terms of resource and performance depending on the number of input/output signals, their width and the number of supported configurations. Experimental results, conducted on an Intel Cyclone V FPGA, compare Ï -P2P to an equivalently functional non-DPR solution called μ-P2P and to a full crossbar. They show that Ï -P2P is indeed lightweight but introduces performance limitations on operating frequency, memory footprint and reconfiguration time. However, Ï -P2P is in general the least resource intensive of the tested interconnects, except in the trivial case of low numbers of signals and configurations. In particular, an 18 à 18 full crossbar interconnect requires 75% more resources than an equivalent Ï -P2P. Interestingly, this resource difference between Ï -P2P and a full crossbar grows linearly with the interconnect size.