Università degli Studi di Cagliari
Carlo Sau
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators
2023-01-01 Ratto, F.; Mainez, A. P.; Sau, C.; Meloni, P.; Deriu, G.; Delucchi, S.; Massa, M.; Raffo, L.; Palumbo, F.
Multithread Accelerators on FPGAs: A Dataflow-Based Approach
2022-01-01 Ratto, F.; Esposito, S.; Sau, C.; Raffo, L.; Palumbo, F.
Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators
2021-01-01 Ratto, Francesco; Fanni, Tiziana; Raffo, Luigi; Sau, Carlo
Runtime adaptive iomt node on multi-core processor platform
2021-01-01 Scrugli, M. A.; Meloni, P.; Sau, C.; Raffo, L.
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project
2021-01-01 Sau, C.; Rinaldi, C.; Pomante, L.; Palumbo, F.; Valente, G.; Fanni, T.; Martinez, M.; van der Linden, F.; Basten, T.; Geilen, M.; Peeren, G.; Kadlec, J.; Jaaskelainen, P.; Bulej, L.; Barranco, F.; Saarinen, J.; Santti, T.; Zedda, M. K.; Sanchez, V.; Nikkhah, S. T.; Goswami, D.; Amat, G.; Marsik, L.; van Helvoort, M.; Medina, L.; Al-Ars, Z.; de Beer, A.
The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design
2021-01-01 Sau, C.; Fanni, T.; Rubattu, C.; Raffo, L.; Palumbo, F.
A Composable Monitoring System for Heterogeneous Embedded Platforms
2021-01-01 Valente, G.; Fanni, T.; Sau, C.; Mascio, T. D.; Pomante, L.; Palumbo, F.
Layering the monitoring action for improved flexibility and overhead control: Work-in-progress
2020-01-01 Valente, G.; Fanni, T.; Sau, C.; Di Battista, F.
NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning
2020-01-01 Nasser, Y.; Sau, C.; Prevotet, J. -C.; Fanni, T.; Palumbo, F.; Helard, M.; Raffo, L.
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project
2020-01-01 Pomante, Luigi; Palumbo, Francesca; Rinaldi, Claudia; Valente, Giacomo; Sau, Carlo; Fanni, Tiziana; Linden, Frank van der; Basten, Twan; Geilen, Marc; Peeren, Geran; Kadlec, Jiri; Jaaskelainen, Pekka; Martinez, Marcos; Saarinen, Jukka; Santti, Tero; Zedda, Maria Katiuscia; Sanchez, Victor; Goswami, Dip; Al-Ars, Zaid; Beer, Ad de
Feasibility study and porting of the damped least square algorithm on FPGA
2020-01-01 Sau, C.; Fanni, T.; Rubattu, C.; Fanni, L.; Raffo, L.; Palumbo, F.
Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI
2019-01-01 Fanni, Tiziana; Madroñal, Daniel; Rubattu, Claudio; Sau, Carlo; Palumbo, Francesca; Juárez, Eduardo; Pelcat, Maxime; Sanz, Cesar; Raffo, Luigi
Reconfigurable and approximate computing for video coding
2019-01-01 Palumbo, Francesca; Sau, Carlo
An integrated hardware/software design methodology for signal processing systems
2019-01-01 Li, L.; Sau, C.; Fanni, T.; Li, J.; Viitanen, T.; Christophe, F.; Palumbo, F.; Raffo, L.; Huttunen, H.; Takala, J.; Bhattacharyya, S. S.
Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators
2019-01-01 Rubattu, Claudio; Palumbo, Francesca; Sau, Carlo; Salvador, Ruben; Serot, Jocelyn; Desnos, Karol; Raffo, Luigi; Pelcat, Maxime
Neu Pow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology
2019-01-01 Nasser, Y.; Sau, C.; Prevotet, J. -C.; Fanni, T.; Palumbo, F.; Helard, M.; Raffo, L.
Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding
2019-01-01 Sau, C.; Ligas, D.; Fanni, T.; Raffo, L.; Palumbo, F.
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems
2018-01-01 Fanni, T; Rodriguez, A; Sau, C; Suriano, L; Palumbo, F; Raffo, L; de la Torre, E
Hardware design methodology using lightweight dataflow and its integration with low power techniques
2017-01-01 Fanni, Tiziana; Li, L; Viitanen, T; Sau, Carlo; Xie, R; Palumbo, F; Raffo, L; Huttunen, H; Takala, J; Bhattacharyya, Ss
Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing
2017-01-01 Sau, Carlo; Palumbo, Francesca; Pelcat, M; Heulot, J; Nogues, E; Menard, D; Meloni, Paolo; Raffo, Luigi
Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy
2017-01-01 Palumbo, Francesca; Fanni, Tiziana; Sau, Carlo; Meloni, Paolo
Dataflow based design suite for the development and management of multi-functional reconfigurable systems
2016-03-30
Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC
2016-01-01 Palumbo, Francesca; Sau, Carlo; Evangelista, Davide; Meloni, Paolo; Pelcat, Maxime; Raffo, Luigi
Demo: Reconfigurable Platform Composer Tool
2016-01-01 Sau, C.; Fanni, T.; Meloni, P.; Raffo, L.; Pelcat, M.; Palumbo, F.
Adaptable AES implementation with power-gating support
2016-01-01 Banik, Subhadeep; Bogdanov, Andrey; Fanni, Tiziana; Sau, Carlo; Raffo, Luigi; Palumbo, Francesca; Regazzoni, Francesco
Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design
2016-01-01 Sau, Carlo; Carta, N; Raffo, Luigi; Palumbo, Francesca
Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures
2016-01-01 Palumbo, Francesca; Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi
SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract
2016-01-01 Palumbo, Francesca; Sau, Carlo; Fanni, Tiziana; Meloni, Paolo; Raffo, Luigi
Power and clock gating modelling in coarse grained reconfigurable systems
2016-01-01 Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca
Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain
2016-01-01 Sau, Carlo; Fanni, L; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca
Automated Design Flow for Multi-Functional Dataflow-Based Platforms
2016-01-01 Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca; Bezati, E; Casale Brunet, S; Mattavelli, M.
Automated power gating methodology for dataflow-based reconfigurable systems
2015-01-01 Fanni, Tiziana; Sau, Carlo; Raffo, Luigi; Palumbo, Francesca
Computing swarms for self-adaptiveness and self-organizationin floating-point array processing
2015-01-01 Pani, Danilo; Sau, Carlo; Palumbo, F; Raffo, Luigi
Coarse-grained reconfiguration: dataflow-based power management
2015-01-01 Palumbo, Francesca; Sau, Carlo; Raffo, Luigi
Power modelling for saving strategies in coarse grained reconfigurable systems
2015-01-01 Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case
2014-01-01 Sau, Carlo; Raffo, Luigi; Palumbo, Francesca; Bezati, E; Casale Brunet, S; Mattavelli, M.
Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units
2014-01-01 Sau, Carlo; Palumbo, Francesca
Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy
2014-01-01 Palumbo, Francesca; Sau, Carlo; Raffo, Luigi
A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool
2013-01-01 Carta, N; Sau, Carlo; Palumbo, Francesca; Pani, Danilo; Raffo, Luigi
A coarse-grained reconfigurable approach for low-power spike sorting architectures
2013-01-01 Carta, N; Sau, Carlo; Pani, Danilo; Palumbo, Francesca; Raffo, Luigi
DSE and profiling of multi-context coarse-grained reconfigurable systems
2013-01-01 Palumbo, Francesca; Sau, Carlo; Raffo, Luigi
A nature-inspired adaptive floating-point coprocessing system
2012-01-01 Sau, Carlo; Pani, Danilo; Palumbo, Francesca; Raffo, Luigi
| Titolo | Data di pubblicazione | Autore(i) | Rivista | Editore |
|---|---|---|---|---|
| An Automated Design Flow for Adaptive Neural Network Hardware Accelerators | 1-gen-2023 | Ratto, F.; Mainez, A. P.; Sau, C.; Meloni, P.; Deriu, G.; Delucchi, S.; Massa, M.; Raffo, L.; Palumbo, F. | JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY | - |
| Multithread Accelerators on FPGAs: A Dataflow-Based Approach | 1-gen-2022 | Ratto, F.; Esposito, S.; Sau, C.; Raffo, L.; Palumbo, F. | - | - |
| Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators | 1-gen-2021 | Ratto, Francesco; Fanni, Tiziana; Raffo, Luigi; Sau, Carlo | ELECTRONICS | - |
| Runtime adaptive iomt node on multi-core processor platform | 1-gen-2021 | Scrugli, M. A.; Meloni, P.; Sau, C.; Raffo, L. | ELECTRONICS | - |
| Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project | 1-gen-2021 | Sau, C.; Rinaldi, C.; Pomante, L.; Palumbo, F.; Valente, G.; Fanni, T.; Martinez, M.; van der Linden, F.; Basten, T.; Geilen, M.; Peeren, G.; Kadlec, J.; Jaaskelainen, P.; Bulej, L.; Barranco, F.; Saarinen, J.; Santti, T.; Zedda, M. K.; Sanchez, V.; Nikkhah, S. T.; Goswami, D.; Amat, G.; Marsik, L.; van Helvoort, M.; Medina, L.; Al-Ars, Z.; de Beer, A. | MICROPROCESSORS AND MICROSYSTEMS | - |
| The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design | 1-gen-2021 | Sau, C.; Fanni, T.; Rubattu, C.; Raffo, L.; Palumbo, F. | MICROPROCESSORS AND MICROSYSTEMS | - |
| A Composable Monitoring System for Heterogeneous Embedded Platforms | 1-gen-2021 | Valente, G.; Fanni, T.; Sau, C.; Mascio, T. D.; Pomante, L.; Palumbo, F. | ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS | - |
| Layering the monitoring action for improved flexibility and overhead control: Work-in-progress | 1-gen-2020 | Valente, G.; Fanni, T.; Sau, C.; Di Battista, F. | - | Institute of Electrical and Electronics Engineers Inc. |
| NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning | 1-gen-2020 | Nasser, Y.; Sau, C.; Prevotet, J. -C.; Fanni, T.; Palumbo, F.; Helard, M.; Raffo, L. | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | - |
| Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project | 1-gen-2020 | Pomante, Luigi; Palumbo, Francesca; Rinaldi, Claudia; Valente, Giacomo; Sau, Carlo; Fanni, Tiziana; Linden, Frank van der; Basten, Twan; Geilen, Marc; Peeren, Geran; Kadlec, Jiri; Jaaskelainen, Pekka; Martinez, Marcos; Saarinen, Jukka; Santti, Tero; Zedda, Maria Katiuscia; Sanchez, Victor; Goswami, Dip; Al-Ars, Zaid; Beer, Ad de | - | - |
| Feasibility study and porting of the damped least square algorithm on FPGA | 1-gen-2020 | Sau, C.; Fanni, T.; Rubattu, C.; Fanni, L.; Raffo, L.; Palumbo, F. | IEEE ACCESS | - |
| Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI | 1-gen-2019 | Fanni, Tiziana; Madroñal, Daniel; Rubattu, Claudio; Sau, Carlo; Palumbo, Francesca; Juárez, Eduardo; Pelcat, Maxime; Sanz, Cesar; Raffo, Luigi | - | - |
| Reconfigurable and approximate computing for video coding | 1-gen-2019 | Palumbo, Francesca; Sau, Carlo | - | IET |
| An integrated hardware/software design methodology for signal processing systems | 1-gen-2019 | Li, L.; Sau, C.; Fanni, T.; Li, J.; Viitanen, T.; Christophe, F.; Palumbo, F.; Raffo, L.; Huttunen, H.; Takala, J.; Bhattacharyya, S. S. | JOURNAL OF SYSTEMS ARCHITECTURE | - |
| Dataflow-functional high-level synthesis for coarse-grained reconfigurable accelerators | 1-gen-2019 | Rubattu, Claudio; Palumbo, Francesca; Sau, Carlo; Salvador, Ruben; Serot, Jocelyn; Desnos, Karol; Raffo, Luigi; Pelcat, Maxime | IEEE EMBEDDED SYSTEMS LETTERS | - |
| Neu Pow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology | 1-gen-2019 | Nasser, Y.; Sau, C.; Prevotet, J. -C.; Fanni, T.; Palumbo, F.; Helard, M.; Raffo, L. | - | Association for Computing Machinery, Inc |
| Reconfigurable Adaptive Multiple Transform Hardware Solutions for Versatile Video Coding | 1-gen-2019 | Sau, C.; Ligas, D.; Fanni, T.; Raffo, L.; Palumbo, F. | IEEE ACCESS | - |
| Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems | 1-gen-2018 | Fanni, T; Rodriguez, A; Sau, C; Suriano, L; Palumbo, F; Raffo, L; de la Torre, E | - | IEEE |
| Hardware design methodology using lightweight dataflow and its integration with low power techniques | 1-gen-2017 | Fanni, Tiziana; Li, L; Viitanen, T; Sau, Carlo; Xie, R; Palumbo, F; Raffo, L; Huttunen, H; Takala, J; Bhattacharyya, Ss | JOURNAL OF SYSTEMS ARCHITECTURE | - |
| Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing | 1-gen-2017 | Sau, Carlo; Palumbo, Francesca; Pelcat, M; Heulot, J; Nogues, E; Menard, D; Meloni, Paolo; Raffo, Luigi | IEEE EMBEDDED SYSTEMS LETTERS | - |
| Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy | 1-gen-2017 | Palumbo, Francesca; Fanni, Tiziana; Sau, Carlo; Meloni, Paolo | JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY | - |
| Dataflow based design suite for the development and management of multi-functional reconfigurable systems | 30-mar-2016 | - | - | Università degli Studi di Cagliari |
| Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC | 1-gen-2016 | Palumbo, Francesca; Sau, Carlo; Evangelista, Davide; Meloni, Paolo; Pelcat, Maxime; Raffo, Luigi | - | Elsevier B.V. |
| Demo: Reconfigurable Platform Composer Tool | 1-gen-2016 | Sau, C.; Fanni, T.; Meloni, P.; Raffo, L.; Pelcat, M.; Palumbo, F. | - | IEEE Computer Society |
| Adaptable AES implementation with power-gating support | 1-gen-2016 | Banik, Subhadeep; Bogdanov, Andrey; Fanni, Tiziana; Sau, Carlo; Raffo, Luigi; Palumbo, Francesca; Regazzoni, Francesco | - | Association for Computing Machinery, Inc |
| Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design | 1-gen-2016 | Sau, Carlo; Carta, N; Raffo, Luigi; Palumbo, Francesca | JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY | - |
| Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures | 1-gen-2016 | Palumbo, Francesca; Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi | JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING | - |
| SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract | 1-gen-2016 | Palumbo, Francesca; Sau, Carlo; Fanni, Tiziana; Meloni, Paolo; Raffo, Luigi | - | Institute of Electrical and Electronics Engineers Inc. |
| Power and clock gating modelling in coarse grained reconfigurable systems | 1-gen-2016 | Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca | - | ACM |
| Reconfigurable Coprocessors Synthesis in the MPEG-RVC Domain | 1-gen-2016 | Sau, Carlo; Fanni, L; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca | - | IEEE |
| Automated Design Flow for Multi-Functional Dataflow-Based Platforms | 1-gen-2016 | Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca; Bezati, E; Casale Brunet, S; Mattavelli, M. | JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY | - |
| Automated power gating methodology for dataflow-based reconfigurable systems | 1-gen-2015 | Fanni, Tiziana; Sau, Carlo; Raffo, Luigi; Palumbo, Francesca | - | Association for Computing Machinery |
| Computing swarms for self-adaptiveness and self-organizationin floating-point array processing | 1-gen-2015 | Pani, Danilo; Sau, Carlo; Palumbo, F; Raffo, Luigi | ACM TRANSACTIONS ON AUTONOMOUS AND ADAPTIVE SYSTEMS | - |
| Coarse-grained reconfiguration: dataflow-based power management | 1-gen-2015 | Palumbo, Francesca; Sau, Carlo; Raffo, Luigi | IET COMPUTERS & DIGITAL TECHNIQUES | - |
| Power modelling for saving strategies in coarse grained reconfigurable systems | 1-gen-2015 | Fanni, Tiziana; Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca | - | IEEE (Institute of Electrical and Electronics Engineers) |
| Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case | 1-gen-2014 | Sau, Carlo; Raffo, Luigi; Palumbo, Francesca; Bezati, E; Casale Brunet, S; Mattavelli, M. | - | IEEE |
| Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units | 1-gen-2014 | Sau, Carlo; Palumbo, Francesca | - | IEEE |
| Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy | 1-gen-2014 | Palumbo, Francesca; Sau, Carlo; Raffo, Luigi | - | IEEE |
| A coarse-grained reconfigurable wavelet denoiser exploiting the multi-dataflow composer tool | 1-gen-2013 | Carta, N; Sau, Carlo; Palumbo, Francesca; Pani, Danilo; Raffo, Luigi | - | IEEE |
| A coarse-grained reconfigurable approach for low-power spike sorting architectures | 1-gen-2013 | Carta, N; Sau, Carlo; Pani, Danilo; Palumbo, Francesca; Raffo, Luigi | - | Institute of Electrical and Electronics Engineers (IEEE) |
| DSE and profiling of multi-context coarse-grained reconfigurable systems | 1-gen-2013 | Palumbo, Francesca; Sau, Carlo; Raffo, Luigi | - | IEEE |
| A nature-inspired adaptive floating-point coprocessing system | 1-gen-2012 | Sau, Carlo; Pani, Danilo; Palumbo, Francesca; Raffo, Luigi | - | IEEE |
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