On-FPGA real-time processing of biological signals from high-density MEAs: A design space exploration

Seu, Giovanni Pietro;Tuveri, Giuseppe;Raffo, Luigi;Meloni, Paolo
2017-01-01

Abstract

High-density microelectrode arrays (HDMEAs) are promising tools to tackle fundamental questions in neuroscience and brain diseases with unprecedented experimental capabilities. The acquisition of the biological signals sampled by such MEAs, that usually involves filtering, preliminary processing and finally data storage, is an intrinsically parallel and computation-intensive activity, particularly in systems targeting thousands of recording channels acquired with sub-millisecond time resolution. Within several applications, these operations need to be performed in real-time. A promising solution offering an adequate performance level relies on parallel hardware structures, making FPGA devices the perfect target technology.\\In this paper, we present an evaluation of an acquisition and processing system, to be implemented on an FPGA device, which is conceived to be connected to multi-channel CMOS-MEAs and is specifically designed for in-vitro and in-vivo recordings of neural activity. The template, implemented on reconfigurable logic, performs the first steps of the computing chain: filtering and adaptive detection of neural spikes. The filtered samples together with information regarding the presence of spikes are stored in an external DDR memory, for further elaboration and communication with the external environment. We performed a design space exploration measuring resource utilization and precision of the detection algorithm for different use-cases, corresponding to different state-of-the-art HDMEAs, and for different application parameters, such as the filtering scheme, number of parallel input channels, and sampling frequency. A prototype instance of the proposed platform, implemented on a low-end Xilinx Zynq SoC, allows to process more than 1 Gbps of data coming from up to 4096 18-kHz channels, within a time latency of 1.8 ms.
2017
Inglese
Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017
9781538634080
Institute of Electrical and Electronics Engineers Inc.
Seu, Giovanni Pietro
175
183
9
31st IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017
Esperti anonimi
2017
usa
internazionale
scientifica
FPGA; MEA; neural networks; signal processing; Hardware and Architecture; Computer Networks and Communications; Information Systems
no
4 Contributo in Atti di Convegno (Proceeding)::4.1 Contributo in Atti di convegno
Seu, Giovanni Pietro; Angotzi, Gian Nicola; Tuveri, Giuseppe; Raffo, Luigi; Berdondini, Luca; Maccione, Alessandro; Meloni, Paolo
273
7
4.1 Contributo in Atti di convegno
none
info:eu-repo/semantics/conferencePaper
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