A custom MPSoC architecture with integrated power management for real-time neural signal decoding

Carta N;MELONI, PAOLO;TUVERI, GIUSEPPE;PANI, DANILO;RAFFO, LUIGI

2014-01-01

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Abstract

Bioengineering research is posing hard challenges to digital embedded system designers. Tight real-time constraints, miniaturization, and low power are critical issues exacerbated by applications requiring the implant of electronic devices in the patient's body. Among them, neurocontrolled motor prostheses are on the cutting edge of the research in the field, requiring the real-time neural signal decoding to extract the patient's movement intention in order to control the mechatronic device. Despite the literature in the field, how to implement a highly-portable and reliable integrated platform is still an open question. In this paper, we propose a field-programmable gate array-based prototype of an multi-processor system-on-chip embedded architecture that implements an online neural signal decoding algorithm. The prototype is capable of respecting the real-time constraints posed by the application when clocked at less than 50 MHz. Considering that the application workload is extremely data dependent and unpredictable, the architecture has to be dimensioned taking into account critical worst-case operating conditions to ensure robustness. To compensate the resulting over-provisioning of the system architecture, a software-controllable power management has been integrated. Experimental results demonstrate the real-time behavior and allow evaluating the usefulness of the proposed power management technique on public databases.