Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy

PALUMBO, FRANCESCA;FANNI, TIZIANA;SAU, CARLO;MELONI, PAOLO
2017-01-01

Abstract

Modern embedded systems, to accommodate different applications or functionalities over the same substrate and provide flexibility at the hardware level, are often resource redundant and, consequently, power hungry. Therefore, dedicated design frameworks are required to implement efficient runtime reconfigurable platforms. Such frameworks, to challenge this scenario, need also to offer application specific support for power management. In this work, we adopt dataflow specifications as a starting point to feature power minimization in coarse-grained reconfigurable embedded systems. The proposed flow is composed of two subsequent steps: 1) the characterization of the optimal topological system specification(s) and 2) the identification of disjointed logic regions. These latter are then used to implement clock and power gating methodologies. The validity of this model-based approach has been proved over the reconfigurable computing core of a multi-functional coprocessor for image processing applications. Results have been assessed targeting both an ASIC 90 nm technology and a 45 nm one.
2017
45 nm CMOS; 90 nm CMOS; Clock gating; Coarse-grained reconfiguration; Common Power Format; Dataflow; MPEG-RVC; Power gating; Power management; Control and Systems Engineering; Modeling and Simulation; Hardware and Architecture; Information Systems; Signal Processing; Theoretical Computer Science
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