Automated Design Flow for Multi-Functional Dataflow-Based Platforms

SAU, CARLO;MELONI, PAOLO;RAFFO, LUIGI;PALUMBO, FRANCESCA;
2016-01-01

Abstract

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application complexities increase year after year. As a consequence, the design process is both time and resource demanding. System configuration along with resources management and mapping remain one of the most challenging problem, particularly when runtime adaptation is required. In this direction, the ISO/IEC SC29WG11 committee (MPEG) has developed the so called MPEG-RVC standards ISO/IEC 23001-4 and 23002-4. This standard provides specifications of video codecs in the form of dataflow programs. In this paper, an integrated design flow to derive optimized multi-functional platforms directly from disjoined high-level specifications is presented. To the authors’ best of knowledge, such an optimization, synthesis and mapping methodology for coarse-grained reconfigurable systems design does not exist within the MPEG-RVC framework. The design flow presented in this paper leverages on an integrated set of independently designed tools, all supporting the RVC standard. Results assessment has been carried out on three different scenarios: an MPEG-RVC decoder, a standard baseline MPEG-RVC JPEG codec and a generalized reconfigurable multi-quality JPEG encoder. For all these scenarios, the proposed design flow has been targeted for a Xilinx Virtex 5 FPGA. Results show how this approach is capable of yielding a reconfigurable design that preserves the original performance of the stand alone non-reconfigurable platform providing, at the same time, considerable area savings featuring a larger set of functionalities. Moreover, platforms programmability, on the basis of the required functionality ID, is automatically handled at runtime without any designer effort.
2016
2015
Inglese
85
1
143
165
23
http://www.springerlink.com/content/1939-8018
Esperti anonimi
internazionale
scientifica
Coarse-grained reconfiguration; Dataflow; ITU-T.IS 1091; JPEG codec; MDC; MPEG-RVC; Multi-functional; Multi-mode; RVC Intra MPEG-4 SP; RVC MPEG-4 SP decoder; TURNUS; Xronos; Control and Systems Engineering; Modeling and Simulation; Hardware and Architecture; Information Systems; Signal Processing; Theoretical Computer Science
Sau, Carlo; Meloni, Paolo; Raffo, Luigi; Palumbo, Francesca; Bezati, E; Casale Brunet, S; Mattavelli, M.
1.1 Articolo in rivista
info:eu-repo/semantics/article
1 Contributo su Rivista::1.1 Articolo in rivista
262
7
reserved
Files in This Item:
File Size Format  
2015_SPS_SAMOS.pdf

Solo gestori archivio

Type: versione post-print
Size 2.7 MB
Format Adobe PDF
2.7 MB Adobe PDF & nbsp; View / Open   Request a copy

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

Questionnaire and social

Share on:
Impostazioni cookie