Current Position: Francesca Palumbo is currently Assistant Professor at the at the University of Sassari in the PolComIng Department within the Information Engineering Unit.

Email: fpalumbo@uniss.it

Address: Viale Mancini 5, 07100 Sassari

Research Area: 09/E3 Electronics, ING-INF 01

Academic education:

• PhD in Electronic Engineering and Computer Science, University of Cagliari (Cagliari, Italy) October 2006 – March 2010
  Thesis title: “Communication-Centric Approach to Multi-Processors System on Chip Design: Interconnection Networks Design and Evaluation “
• Master Advanced in Embedded System Design, Advanced Learning and Research Institute, University of Lugano (Lugano, Switzerland), September 2005 – July 2006           Thesis title: “Power Analysis Attacks: current possibilities and future prospective”
• Master of Science in Electronic Engineering, University of Cagliari (Cagliari, Italy), September 2003 – April 2005
  Thesis title: “HDL modelling, implementation on silicon and power dissipation evaluation of Network-on-Chip modules”
• Bachelor in Electronic Engineering, University of Cagliari (Cagliari, Italy), September 1999 – October 2003
  Thesis title: “Studio e implementazione su DSP TMS320VC5402 di un filtro per la rivelazione di un segnale vocale nascosto da intenso rumore di fondo “

Research Interest: The research activities/interests of Dr. Palumbo focus mainly on the development of advanced computer systems, with particular emphasis at the moment on hardware/software co-design methodologies and tools for multi-media technologies. In the past, Dr. Palumbo has worked on communication-based systems.

Multimedia digital technologies led to the development of complex systems to create, use and share audio/video/image contents. Consequently standards are increasingly more complex and require the integration, on the same support, of incredibly more functionalities to be served in real-time. To be competitive on the market, it is necessary to bridge the gap between the physical development of the system and the mapping of such functionalities on it.

Dr. Palumbo, in cooperation with the École Polytechnique Fédérale de Lausanne (CH) and the Institute of Electronics and Telecommunications de Rennes (FR), has designed and engineered a development framework for coarse-grained reconfigurable hardware platforms, the Multi-Dataflow Composer tool. This dataflow-based design framework allows the automating mapping and programmability of several different high-level specifications of a coarse-grained reconfigurable substrate. Run-time reconfigurability and power management are handled automatically by the tool.

Projects:

• 2006-2009 “SHAPES – Scalable Software Hardware Architecture Platform for Embedded Systems”, European FP6 Project (IST-FET-26285)
• 2010-2013 “MADNESS – Methods for predictAble Design of heterogeNeous Embedded System with adaptivity and reliability support”, European FP7 Project (n. 248424).
• 2007-2012 “ALBA – Elaborazione riconfigurabile a bassa dissipazione di potenza per digital signal processing”, National FAR Project (D.LGS. 297/1999 –MIUR)
• 2010-2012 “FORCE – Framework di Ottimizzazione per Reti di Interconnessione communication-CEntric: ideazione di soluzioni innovative per sistemi multiprocessore on-chip”, Sardinian Regional Project (LR 7 agosto 2007, n. 7)
• 2012-2014 “RPCT (Reconfigurable Platform Composer Tool”, Sardinian Regional Project (LR 7 agosto 2007, n. 7)

International research collaborations:

Within her research activity Dr Palumbo personally and directly cooperates on a daily bases with researches from first-class academic and industrial factors in the field of Electronic Engineering:

• SHAPES related activities
  • STMicroelectonics [Grenoble]
  • Università degli Studi di Pisa
  • RWTH Aachen University
  • ATMEL Roma
  • INFN Roma
• ALBA related activities
  • STMicroelectonics [Catania]
  • Università degli Studi di Bologna
• RPCT related activities
  • École Polytechnique Fédérale de Lausanne
  • IETR-INSA Institute of Electronics and Telecommunications of Rennes
  • Synflow SAS [Rennes, FRANCE]

Awards

• BEST PAPER AWARD – F. Palumbo, N. Carta, L. Raffo, “The Multi-Dataflow Composer tool: a runtime reconfigurable platform composer”, Conference on Design and Architectures for Signal and Image Processing (DASP 2011), pp. 178-185, Tampere (Finland), 2-4 November 2011

Steering/Technical/Organization Committee

• ACM International Conference on Computing Frontiers (CF)
  • Since 2014 Member of the Steering Committee
  • Member of the Organization Committee
    • CF 12 – 15-17/05/2012, Cagliari (ITA) – Local Co-Chair and Session Chair on Energy Efficiency
    • CF 13 – 14-16/05/2013, Ischia (ITA) – Posters e Workshop/Demo Co-Chair
    • CF 14 – 20-22/05/2014, Cagliari (ITA) – Local Chair
    • CF 15 – 18-21/05/2015, Ischia (ITA) – Workshop / Industry Sessions Chair
  • Conference on Design and Architectures for Signal and Image Processing (DASIP):
    • Member of the Technical Program Committee
      • DASIP 2011 – 2-4/11/2011, Tampere (FIN)
      • DASIP 2012 – 23-25/10/2012, Karlsruhe (DE)
      • DASIP 2013 – 8-10/10/2013, Cagliari (ITA)
      • DASIP 2014 – 8-10/10/2014, Madrid (ES)
    • Member of the Organization Committee
      • DASIP 2012 – 23-25/10/2012, Karlsruhe (DE) – Session Chair on Application-specific Processor and Co-processors for Image and Signal Processing
      • DASIP 2013 – 8-10/10/2013, Cagliari (ITA) – Demo Night Co-Chair and Session Chair on Tools for DSP Algorithm Implementation
    • International Symposium on Image and Signal Processing and Analysis (ISPA)
      • Member of the Organization Committee
        • ISPA 2013 – 4-6/09/2013, Trieste (ITA) – Organizer and Co-Chair of the Special Session on Hardware-software co-design methodologies for streaming processing in Digital Media Technologies

Teaching Activity

• Lecturer Activity
  • AY: 2010-2011 Course: “Architectures and Systems for DSP”, second module of the Embedded Systems Course (30 hours, ING-INF/01) Department: Dept of Electronic Engineering, Electronics Engineering Degree, UNICA

• AY: 2012-2013 and 2013-2014 Course: “Digital Electronics”, second module of the Biomedical Equipment 1 Course (50 hours, ING-INF/06) Department: Dept of Electronic Engineering, Biomedical Engineering Degree, UNICA

• Teaching assistant activity:
  • AY: 2006-2007-2008-2009-2010 Course: Embedded Systems Course (ING-INF/01), Department: Dept of Electronic Engineering, Electronics Engineering Degree, UNICA

• AY: 2006-2007 Course: Electronics Course (ING-INF/01) Department: Dept of Mathematical Sciences, Physics and Informatics, Informatics Degree, UNICA

• Master Thesis co-advising
  • Master of Science
    • Carlo Sau, “Studio ed implementazione su FPGA di un architettura bio-ispirata in virgola mobile per Digital Signal Processing”, 2011/2012
    • Sergio Diana, “Prototipazione su FPGA di un layer di comunicazione dual-mode per sistemi multi-core”, 2011/2012
    • Emanuele Manca, “Studio e sviluppo di un tool per la generazione automatica di piattaforme hardware riconfigurabili”, 2010/2011
    • Andrea Deidda, “Studio e Implementazione RTL di una NoC dual-mode con gestione non esclusiva e programmabile dei Link”, 2010/2011
    • Andrea Congiu, “Codifica HDL, valutazione delle prestazioni e caratterizzazione su tecnologia CMOS 90 nm di una NoC ibrida”, 2010/2011
    • Alessandro Pilia, “Ottimizzazione e validazione di una Network-on-Chip dual-mode per un traffico eterogeneo”, 2009/2010
    • Mauro Pisano, “Studio e implementazione SystemC TLM di un router per una Network on Chip Spidergon-like”, 2007/2008
    • Alessandro Paschina, “Sviluppo e implementazione di Adapters RTL/TLM per protocolli STBus-Network on chip e DNP-Network on Chip su reti Spidergon-like in SystemC”, 2007/2008
    • Simone Sechi, “Studio, modellizzazione RTL e simulazione di un single-chip massively parallel processor adattativo a controllo semi-distribuito”, 2006/2007
  • Bachelor
    • Francesco Dessy, “Architetture hardware per filtri riprogrammabili in applicazioni neurali”, 2013/2014
    • Daniel Melis, “Studio e progettazione di un front-end generalizzato per coprocessore riconfigurabile multi-standard”, 2013/2014
    • Riccardo Montano, “Sviluppo su FPGA di un memory-manager per l’ottimizzazione dell’accesso alla memoria in un coprocessore bio-ispirato”, 2010/2011
    • Marco Uccheddu, “Ottimizzazione e integrazione FPGA del controller di un coprocessore matematico bio-ispirato”, 2009/2010
  • Theses co-advised in cooperation with foreign institutions:
    • Master of Science
      • Tiziana Fanni, “High level design and automatic optimization of signal processing applications: using next-generation tools”, 2013/2014 in cooperation with the IETR of Rennes