`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 28.02.2019 14:35:25
// Design Name: 
// Module Name: register_file
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module register_file #(
    parameter DATA_SIZE = 32,
    parameter REG_NUM = 1024,
    parameter ADDR_SIZE = $clog2(REG_NUM)
)(
    input clock,
    input reset,
    input wr_en,
    input [4:0] addr_wr,
    input [4:0] addr_rd_1,
    input [4:0] addr_rd_2,
    input [DATA_SIZE-1:0] data_wr,
    output [DATA_SIZE-1:0] data_rd_1,
    output [DATA_SIZE-1:0] data_rd_2
);

    reg [DATA_SIZE-1:0] registers [0:REG_NUM-1];
    
    integer i;
    
    always@(posedge clock or posedge reset)
        if(reset)
            for(i=0;i<REG_NUM;i=i+1)
                registers[i]=0;
        else
            if(wr_en)
                registers[addr_wr] <= data_wr;
            
    assign data_rd_1 = registers[addr_rd_1];
    assign data_rd_2 = registers[addr_rd_2];

endmodule

