`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 28.02.2019 11:57:19
// Design Name: 
// Module Name: sign_extend
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module sign_extend (
    input [31:0] instruction,
    output reg [31:0] data_out
);    
     always@(*)
           casex(instruction[31:21])
               // LDUR OR STUR
               11'b111110000x0:    data_out = {{23{instruction[20]}},instruction[20:12]};
               // CBZ
               11'b10110100xxx:    data_out = {{13{instruction[23]}},instruction[23:5]};
               default:            data_out = 32'bx;
           endcase

endmodule
