`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 28.02.2019 11:29:50
// Design Name: 
// Module Name: alu
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module alu #(
    parameter DATA_SIZE = 32
)(
    input [3:0] opcode,
    input [DATA_SIZE-1:0] op_a,
    input [DATA_SIZE-1:0] op_b,
	input [5:0] shamt,
    output zero,
    output reg [DATA_SIZE-1:0] result
);

    always@(*)
        case(opcode)
            4'b0000:    result = op_a & op_b;
            4'b0001:    result = op_a | op_b;
            4'b0010:    result = op_a + op_b;
			4'b0100:	result = op_a << shamt;
			4'b0101:	result = op_a >> shamt;
            4'b0110:    result = op_a - op_b;
            4'b0111:    result = op_b;
            4'b1100:    result = op_a ^ op_b;
            default:    result = {DATA_SIZE{1'bx}};
        endcase

    assign zero = ~|result;


endmodule
