`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 28.02.2019 15:11:42
// Design Name: 
// Module Name: control
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module control(
    input [10:0] instr_opcode,
    output Reg2Loc,
    output ALUSrc,
    output MemtoReg,
    output RegWrite,
    output MemRead,
    output MemWrite,
    output Branch,
    output [1:0] ALUOp
);

    reg [8:0] outputs;
    
    assign {Reg2Loc,ALUSrc,MemtoReg,RegWrite,MemRead,MemWrite,Branch,ALUOp[1],ALUOp[0]} = outputs;
    
    always@(*)
        casex(instr_opcode)
            // R-format
            11'b1xx0101x000:    begin outputs = 9'b0001000_10; $display("R-format %b",instr_opcode); end
            // LDUR
            11'b11111000010:    begin outputs = 9'bx111100_00; $display("LDUR %b",instr_opcode); end
            // STUR
            11'b11111000000:    begin outputs = 9'b11x0010_00; $display("STUR %b",instr_opcode); end
            // CBZ
            11'b10110100xxx:    begin outputs = 9'b10x0001_01; $display("CBZ %b",instr_opcode); end
            default:            outputs = 9'bx;
        endcase

endmodule
