`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 28.02.2019 15:35:55
// Design Name: 
// Module Name: tb_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_top;

    reg clock;
    reg reset;
    
    top dut (
        .clock(clock),
        .reset(reset)
    );

    always #5 clock = ~clock;
    
    initial
        begin
            clock = 0;
            reset = 0;
            
            #3
            reset = 1;
            
            #50
            reset = 0;
                     
            #1000
            $stop;
        end

endmodule
