`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 28.02.2019 10:31:55
// Design Name: 
// Module Name: register
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module register #(
    parameter DATA_SIZE = 32
)(
    input clock,
    input reset,
    input load,
    input [DATA_SIZE-1:0] data_in,
    output reg [DATA_SIZE-1:0] data_out
);

    always@(posedge clock or posedge reset)
        if(reset)
            data_out <= 0;
        else
            if(load)
                data_out <= data_in;

endmodule
