`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 28.02.2019 15:35:55
// Design Name: 
// Module Name: tb_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_top;

    reg clock;
    reg reset;
	wire [15:0] gpio_A;
    
    top dut (
        .clock(clock),
        .reset(reset),
		.gpio_A(gpio_A)
    );

    always #5 clock = ~clock;
    
    initial
        begin
            clock = 0;
            reset = 0;
            
            #3
            reset = 1;
            
            #50
            reset = 0;
                     
            #1000
            $stop;
        end
		
	assign gpio_A[0] = 1'bz;
	assign gpio_A[1] = 1'bz;
	assign gpio_A[2] = 1'bz;
	assign gpio_A[3] = 1'bz;
	assign gpio_A[4] = 1'bz;
	assign gpio_A[5] = 1'bz;
	assign gpio_A[6] = 1'bz;
	assign gpio_A[7] = 1'bz;
	assign gpio_A[8] = 1'bz;
	assign gpio_A[9] = 1'bz;
	assign gpio_A[10] = 1'bz;
	assign gpio_A[11] = 1'bz;
	assign gpio_A[12] = 1'bz;
	assign gpio_A[13] = 1'bz;
	assign gpio_A[14] = 1'bz;
	assign gpio_A[15] = 1'bz;

endmodule
