University of Cagliari
Francesco Ratto
Showing results 1 to 5 of 5
Design methodologies and architectures for application-specific coarse-grain reconfigurable accelerators
2024-02-15
A multithread AES accelerator for Cyber-Physical Systems
2023-01-01 Ratto, Francesco; Raffo, Luigi; Palumbo, Francesca
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators
2023-01-01 Ratto, F.; Mainez, A. P.; Sau, C.; Meloni, P.; Deriu, G.; Delucchi, S.; Massa, M.; Raffo, L.; Palumbo, F.
Multithread Accelerators on FPGAs: A Dataflow-Based Approach
2022-01-01 Ratto, F.; Esposito, S.; Sau, C.; Raffo, L.; Palumbo, F.
Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators
2021-01-01 Ratto, Francesco; Fanni, Tiziana; Raffo, Luigi; Sau, Carlo
| Title | Issue Date | Author(s) | Journal | Publisher |
|---|---|---|---|---|
| Design methodologies and architectures for application-specific coarse-grain reconfigurable accelerators | 15-Feb-2024 | - | - | Università degli Studi di Cagliari |
| A multithread AES accelerator for Cyber-Physical Systems | 1-Jan-2023 | Ratto, Francesco; Raffo, Luigi; Palumbo, Francesca | - | The Association for Computing Machinery |
| An Automated Design Flow for Adaptive Neural Network Hardware Accelerators | 1-Jan-2023 | Ratto, F.; Mainez, A. P.; Sau, C.; Meloni, P.; Deriu, G.; Delucchi, S.; Massa, M.; Raffo, L.; Palumbo, F. | JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY | - |
| Multithread Accelerators on FPGAs: A Dataflow-Based Approach | 1-Jan-2022 | Ratto, F.; Esposito, S.; Sau, C.; Raffo, L.; Palumbo, F. | - | - |
| Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators | 1-Jan-2021 | Ratto, Francesco; Fanni, Tiziana; Raffo, Luigi; Sau, Carlo | ELECTRONICS | - |
Showing results 1 to 5 of 5
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